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Cloud Based Analog IC Design Hackathon

Hackathon Date: 15 Feb - 8 March 2022
Register Till: 13 February 2022

Registration Closed

Purpose

To provide a basic hands-on understanding of "Analog IC design", which enhances your practical IC design knowledge, helps to innovate, to create state-of-the-art designs, and integrate them into real-world semiconductor applications.

What is Analog IC design hackathon?

IIT Hyderabad in collaboration with Synopsys & VSD wants to generate skilled manpower in the domain of IC design, which will strengthen the decision of the Indian Government for the silicon revolution. The Indian Govt initiative Chips to Startup (C2S) aims to propel innovation, build domestic capacities to ensure hardware sovereignty, and build a Semiconductor Ecosystem that requires 85,000+ highly trained engineers. Working towards this vision statement, we have planned the 3-Week “Cloud based Analog IC Design Hackathon using Synopsys Custom Design Platform”.

Objective

We would like to invite all Indian college students & professionals to explore more about semiconductor designs by participating in this hackathon. Here we will introduce Analog Design concepts and train you to design analog IP using Synopsys tools preinstalled in cloud server.

Timeline




Date Activity Description Session Recorded Video / Report Submission Link
5 Feb - 13 Feb 2022 Registration for the Hackathon Complete the participation form.
15 Feb 2022 Hackathon Inauguration Webinar IITH, Synopsys and VSD will introduce to Synopsys Custom Design Platform and hackathon process.
15 Feb - 18 Feb 2022 Literature Survey Participant needs to research on their interest areas from reputed journals.
19 Feb 2022 Report Submission Participants need to submit the research conclusion and plan on circuit implementation in the prescribed format.

Submit your report here
20 Feb - 26 Feb 2022 Design Implementation Participants need to design, characterize and simulate using Synopsys Custom Design Platform.
27 Feb - 1 Mar 2022 Report Submission and documentation Participants need to upload the reference and actual circuit/waveform using Synopsys Custom Design Platform in pre-defined format.

Submit your Final Report here

8 March 2022 Result Declaration Declared



Who can participate?

  • Only individual participant (no group).
  • Basic electronics knowledge expected.
  • Free Registration.

Problem Statement

  • The participants will use Synopsys iPDK and Synopsys Custom Design Platform to design, simulate and analyze their circuits.

Rules and Regulations

  • The circuit design and simulation has to be done only using Synopsys Custom Design Platform.
  • This hackathon is open only to individuals. We will not accept team or group registration/submissions.
  • Any participant found to be indulging in any form of malpractice will be immediately disqualified.
  • The decision of the review committee and the organizers in declaring the results will be final. No queries in this regard will be entertained.

Resources

System Requirements

  • Tools will be availed to all participants by IIT Hyderabad through cloud server, so the minimum requirements for running the tool are the following:
    • Any OS
    • Any browser
    • Min 4 Mbps internet connection
    • Minimum of 2GB RAM on Laptop/PC

Guidelines

Will be shared periodically through this website or to your registered email.

Benefits

  • e-Certificates will be awarded only to the participants who complete the design successfully.
  • Internship opportunity to participant who successfully complete the design.
  • Interested participant can continue the research and enhance the IP with IITH team support.

Poster

Partners and Organizers

IIT Hyderabad

Ministry of Electronics & IT (MeitY)
Government of India



Synopsys

VLSI System Design