A | B | C | D | E | |
---|---|---|---|---|---|
1
|
List of Desings under Very Good Category | ||||
2
|
Sl No | Full Name | Institute / Organization name | Design Name | Download |
3
|
1 | Aakash K | Cambridge Institute of Technology | 8x4 Barrel Shifter using NMOS Pass Transistor Logic in 28nm Technology node Using Synopsis Tool | Download |
4
|
2 | Abhash Kumar | National Institute of Technology Patna | In-memory-Boolean-Computation-inside-10T-SRAM-Cells | Download |
5
|
3 | Abhishek Sarkar | Jadavpur University | 3-bit Binary to Grey Code Converter using Low Voltage XOR Gates | Download |
6
|
4 | ABISHEK R | MADRAS INSTITUTE OF TECHNOLOGY (ANNA UNIVERSITY) | OPERATIONAL AMPLIFIER | Download |
7
|
5 | Abrar | manipal | Simulation of CMOS based Comparator | Download |
8
|
6 | Aditya Kalyani | Indian Institute of Technology, Dharwad | Design and Analysis of a Fully Differential Two-Stage CMOS Op-Amp with Miller Compensation | Download |
9
|
7 | Akash Arun Ambekar | KIT's College of Engineering, Kolhapur | Implementation of 4-bit Even Parity Generator using CMOS 28-nm Process Technology | Download |
10
|
8 | Akash Gupta | Netaji Subhas University of Technology(NSUT), East Campus | Implementation of 2:4 DEC using 28nm CMOS Technology | Download |
11
|
9 | Akhil D R | NXP Semiconductor | Design Analysis of Conventional Full Adder Architecture on 28nm CMOS Technology | Download |
12
|
10 | Akula Sairam | Indian Institute of Information Technology Allahabad | 4x4 Wallace tree multiplier using Sklansky | Download |
13
|
11 | Alekhya Yalla | Aditya College of Engineering and Technology | Design of 7T SRAM Cell using Supply feedback technique | Download |
14
|
12 | ANAND KUMAR | MNNIT Allahabad | 6T SRAM | Download |
15
|
13 | Anandita | National Institute Of Technology Patna | Differential Amplifier | Download |
16
|
14 | Aniruddha Abhay Joshi | VIT University , Vellore | 4 - Bit Parity Generator | Download |
17
|
15 | ANKIT VIVEK | MOTILAL NEHRU NATIONAL INSTITUTE OF TECHNOLOGY, ALLHABAD,UTTAR PRADESH-211004 | Performance-analysis-of-CMOS-based-one-bit-full-adder-with-DOMINO-based-one-bit-full-adder | Download |
18
|
16 | Anmol Saxena | DA-IICT | A Tree Architecture Based 8-to-1 Serializer | Download |
19
|
17 | Anuj Agrawal | NIT Trichy | Full-Adder-CMOS-design-Using-28nm-pdk | Download |
20
|
18 | ARKA CHAKRABORTY | Jadavpur University | Electronic Buzzer Circuit | Download |
21
|
19 | Arpit Sharma | Inderprastha Engineering College | Implementation of CMOS Schmitt Trigger | Download |
22
|
20 | Arun Narayana Viswanathuni | G Pulla Reddy Engineering College | HV Tolerant Level Shifter using 28nm CMOS | Download |
23
|
21 | Ashutosh kumar | JC Bose UST | Binary to gray converter using transmission Gate | Download |
24
|
22 | Ashwin Rajesh | Government Engineering College, Thrissur | CMOS Schmitt Trigger | Download |
25
|
23 | ATHIRA A K | National Institute of technology Puducherry | Full adder using CMOS | Download |
26
|
24 | Avula Girish Kumar | Defence Institute of Advanced Technology | 9 Stage Ring Oscillator using CMOS | Download |
27
|
25 | Ayush Gupta | SRM Institute of Science and Technology, Kattankulathur | 3T1D Capacitorless DRAM using 28nm CMOS Technology | Download |
28
|
26 | Ayush Kanojia | National Institute of Technology, Delhi | Effective 16T 1-bit Hybrid Full Adder cell | Download |
29
|
27 | Beeraka Venkata Bharadwaj | IIITDM Kancheepuram | Quadruple Cross-Coupled Latch-Based 12T SRAM | Download |
30
|
28 | BEMALKHED AKHILESH | B.V. RAJU INSTITUTE OF TECHNOLOGY | Implementation Of 2:1 Mux Using CMOS | Download |
31
|
29 | Bharat Suthar | Defence Institute of Advanced Technology, Pune | Full Adder Using CMOS Technology | Download |
32
|
30 | bharath g s | bms college of engineering | 6T SRAM CELL | Download |
33
|
31 | BHARGAV VAMSHI MADUPU | B V Raju Institute Of Technology | Low Power CMOS Full Adder | Download |
34
|
32 | Bhawarth Gupta | Bharati Vidyapeeth (Deemed University) College of Engineering, Pune | Low-Noise Voltage Control Ring Oscillator using 28nm Technology node | Download |
35
|
33 | BHUVAN JOSHI | Indian Institute of Space Science and Technology | Design of Gate-Bootstrapped Switch using 28nm Synopsys iPDK | Download |
36
|
34 | BIKRAM KESHARI PANDA | NIT, Jamshedpur | 1 bit Full-Adder circuit with full-swing hybrid style design in 28nm technology | Download |
37
|
35 | CHARAAN S | Madras Institute of Technology, Anna University | Design of a 4x4 Braun Array Multiplier with a 3-bit Kogge-Stone Adder, in 32nm CMOS Process | Download |
38
|
36 | Debjit Batabyal | Indraprastha Institute of Information Technology, Delhi | Memory Read operation using 6T SRAM cell and Conventional Latch type Sense Amplifier | Download |
39
|
37 | Debjyoti Banerjee | NIT DURGAPUR | Low power comparator using CMOS technology | Download |
40
|
38 | Dinesh Patnaik | Self | Latch based Integrated Clock Gating Cell | Download |
41
|
39 | Dipesh Panchal | Nirma University | Bulk Driven Non-Tailed Operational Transconductance Amplifier for Ultra-Low Power Applications | Download |
42
|
40 | Divaker Sharma | Jamia Millia Islamia- A Central University, New Delhi | 10T_BLP_SRAM_Cell | Download |
43
|
41 | Dr. M. Pown | Sri Sai Ram Institute of Technology, Chennai | RF Mixer Circuit Using 28 nm CMOS Technology | Download |
44
|
42 | E Balakrishna | DRONACHARYA GROUP OF INSTITUTION, GREATER NOIDA | Analysis of CMOS Schmitt Trigger using 28nm Technology | Download |
45
|
43 | Eruganti Saikiran | self | single supply level shifter | Download |
46
|
44 | G Victor Swaroop | VNR Vignana Jyothi Institute of Engineering and Technology | Gilbert Cell Multiplier | Download |
47
|
45 | Gaeya Sri Satya Vinnakota | Sardar Vallabhbhai National Institute Of Technology | 4:1 MUX using CMOS Logic | Download |
48
|
46 | GANGULA MARESWARA RAO | UCET, MAHATMA GANDHI UNIVERSITY, NALGONDA | A Partially Static High Frequency 18T Hybrid Topological Flip-Flop Design | Download |
49
|
47 | GANTA TEJ CHARAN | INDIAN INSTITUTE OF INFORMATION TECHNOLOGY, DESIGN AND MANUFACTURING, KANCHEEPURAM | High Speed Low Power CMOS Current Comparator | Download |
50
|
48 | Ghanshyam Verma | IIIT NR | 4-Bit Ripple Carry Adder | Download |
51
|
49 | Glenn Frey Olamit | NA | 4 bit Carry Lookahead Adder | Download |
52
|
50 | Harshit Agarwal | Indian institute of information technology, allahabad | 5-Stage Current starved Voltage controlled oscillator at 28nm technology node | Download |
53
|
51 | INDERJIT SINGH DHANJAL | K. J Somaiya College of Engineering | Design and Simulation of a 4-bit CLA adder using CMOS mirror logic | Download |
54
|
52 | Jessita Joseph | C-DAC | Hybrid 1 Bit Full Adder Using 13 Transistors | Download |
55
|
53 | Kanad Mainkar | Vishwakarma Institute of Technology | Design of a Telescopic Cascode Operational Amplifier | Download |
56
|
54 | Kashish Goyal | Jaypee Institute Of Information Technology, Noida | Low-Power-Voltage-Bandgap-Reference-Circuit-in-28nm-CMOS-Technology | Download |
57
|
55 | Krishna Gupta | Jaypee Institute of Information Technology | Design of a Beta Multiplier Current Reference Circuit in 28nm CMOS Technology | Download |
58
|
56 | Lakshmi Jayani Penumarthy | VIT-AP University | High Speed 16T Full Adder Design using 28nm CMOS Technology | Download |
59
|
57 | LAVANYA MADDISETTI | Self | Design of a Two Stage Operational Amplifier with Miller Compensation | Download |
60
|
58 | M.Kasthoori | Sphoorthy Engineering college ,Nadargul,Hyd.(2021 passed out) | Design-of-28T-cmos-Full_Adder | Download |
61
|
59 | Mahima Goyen | Na | Low Noise Voltage Controlled Ring Oscillator in 28-nm | Download |
62
|
60 | Mahisha B M | R. M. K. Engineering College | 8-bit Carry Select Adder with Binary to Excess One Converter | Download |
63
|
61 | Manoj Kumar Jeeru | Indian Institute of Information Technology Design and Manufacturing Kancheepuram | A Novel Phase Frequency Detector for a High Frequency PLL Design | Download |
64
|
62 | MANOJ KUMAR SINGH | INDIAN INSTITUTE OF INFORMATION TECHNOLOGY,ALLAHABAD | DESIGN OF D- FLIP FLOP USING MASTER SLAVE CONFIGURATION | Download |
65
|
63 | Mansi Shukla | IIIT NAYA RAIPUR | 4-bit binary to gray converter | Download |
66
|
64 | Mayur Vithal Dongre | Indian Institute of Information Technology Nagpur | 28T Full Adder using 28nm CMOS Technology | Download |
67
|
65 | MIDHUN KUMAR V | IIT Delhi | Design of Double-Tail Dynamic Comparator | Download |
68
|
66 | MOHD ABDUL MUQEEM NAWAZ | HCL TECHNOLOGIES | PHYSICAL DESIGN ENGINEER | Download |
69
|
67 | Mritunjay | Panjab University | 9TSRAM Cell | Download |
70
|
68 | Mrs. Madhuri Hemant Kadam | Shree L. R. Tiwari College of Engineering | LVDS Driver Design for High Speed Application | Download |
71
|
69 | Muthulakshmi M | Thiagarajar College of Engineering | Design of 1-bit Full Adder using CMOS | Download |
72
|
70 | Nalinkumar S | Madras Institute of Technology, Anna University | 8x4 Right Barrel Shifter using NMOS Pass Transistor Logic | Download |
73
|
71 | NAMAN KUMAR VERMA | NITK SURATHKAL | Pulse and Sense amplifier based register | Download |
74
|
72 | Naveen Kumar S | Vellore Institute of Technology, Vellore | Low Power and High Speed Voltage Level Shifter Based on Cross Coupled Pull Up Network | Download |
75
|
73 | Naveenkumar K H | VIT, Vellore | A Power-On Reset Circuit with inbuilt Brown-Out Detection Capability using 28nm CMOS Technology | Download |
76
|
74 | NAVYASHREE B R | RV College of Engineering | Design of two stage opamp in 28nm technology | Download |
77
|
75 | Neha Sharma | Indian Institute of Technology Jammu | Dual Interlocked Storage Cell | Download |
78
|
76 | Nikhil Singh | VIT Chennai | Design of Schmitt Trigger Using Domino Logic in 28nm | Download |
79
|
77 | Pambhar Neel Arvindbhai | Vishwakarma Government Engineering College | 4-bit ring counter using cmos 28nm Technology | Download |
80
|
78 | PAVAN KUMAR KORI | PDPM IIITDM JABALPUR | DESIGN BANG GAP REFERENCE WITH STARTUP CIRCUIT | Download |
81
|
79 | PHALGUN G K | R V College Of Engineering | Two Stage Opamp Using Miller Compensation Technique for 28nm Technology | Download |
82
|
80 | Prabhavathi P | B N M Institute of Technology | Design of Low voltage Bandgap Reference in 28nm Technology for Low power applications. | Download |
83
|
81 | Prasanth Mandadi | SELF | Design-of-6T-SRAM-Cell-at-28nm-CMOS-Technology | Download |
84
|
82 | Prateek Sinha | IIT JAMMU | 8T SRAM | Download |
85
|
83 | PREM KUMAR R | CHRIST(Deemed To Be University) | 5 stage 2.92 GHz CMOS Voltage Controlled Oscillator | Download |
86
|
84 | Prince Pandey | IIIT, Allahabad | Current Starved Voltage Controlled Oscillator | Download |
87
|
85 | Priyanka Tiwari | Govt. Engg. College Raipur | Design of High Speed Duty Cycle Corrector with 28 nm technology | Download |
88
|
86 | Pushpal Das | SRM Institute of Science and Technology | 3 bit binary to grey code converter | Download |
89
|
87 | R A Yogeshwaran | Vellore Institute of Technology, Vellore | CMOS one bit Full Adder | Download |
90
|
88 | R.V.Rohinth Ram | Madras Institute of Technology Campus, Anna University | Astable Multivibrator using Operational Amplifier | Download |
91
|
89 | Ramachandra T | Madras Institute of Technology, Anna University | Five Stage Ring Oscillator | Download |
92
|
90 | Rashmi Ranjan Kindal | GIET University, Gunupur | 4 Bit Universal Shift Resistor | Download |
93
|
91 | Reshma SM | CDAC | Comparator Latch | Download |
94
|
92 | Ruchit Chudasama | IIT Gandhinagar | HIGH SPEED LOW VOLTAGE CMOS FULL ADDER VLSI DESIGN | Download |
95
|
93 | Sai venkat Bala badruni | Amrita school of Engineering, Chennai campus | Design of a 4-bit Carry Look-Ahead Adder | Download |
96
|
94 | SAMYAK JAIN | Defence Institute of Advanced Technology | CMOS Full adder for 15-4 Compressor using 28nm Technology | Download |
97
|
95 | Sanket M | RV | Schmitt Trigger in 28nm CMOS Technology | Download |
98
|
96 | Satish Kumar L | NIT Trichy | StrongARM Latch based comparator | Download |
99
|
97 | Shashank Mishra | Jadavpur University | 10-bit Digital to Analog Converter(DAC) | Download |
100
|
98 | Shiva Kumar S | Sapthagiri College of Engineering | 4 : 1 MUX using Transmission Gate | Download |
101
|
99 | Shivani | J.C. Bose UST YMCA | High Performance Binary to Gray Code Converter using Transmission GATE | Download |
102
|
100 | SHUBHAM KUMAR | NIT Patna | 28-T-Full-Adder-using-CMOS | Download |
103
|
101 | SHUBHAM VENKATESH SHRIRAM | Working | Low Power 8T SRAM using Cell Approach | Download |
104
|
102 | Sidhant Priyadarshi | Kle technological University | 2-bit random number generation and data encryption | Download |
105
|
103 | SIRIGIBATTULA KEERTANA | Vellore Institute of Technology,Vellore | AREA EFFICIENT MODIFIED ARRAY MULTIPLIER | Download |
106
|
104 | Sisir Pynda | Vellore Institute of Technology, Vellore | Full Adder Design Using CMOS | Download |
107
|
105 | Sresthavadhani Mantha | International Institute of Information Technology | Implementing a Bang Bang Phase Detector in 28nm CMOS Technology | Download |
108
|
106 | Subhasish Banerjee | MCKV Institute of Engineering | Design of a Single Stage Amplifier with 1 MHz Bandwidth, 25dB Gain and 50 µA Quiescent Current in 28nm CMOS Technology using Synopsys Custom Design Platform | Download |
109
|
107 | Sudhee Bhat | Dayananda Sagar College of Engineering | A 7T SRAM Cell using Supply Feedback Technique | Download |
110
|
108 | Sumanto Kar | FOSSEE, IIT Bombay | Feynman Gate | Download |
111
|
109 | Supritha Bekal | Mangalore Institute Of Technology & Engineering, Moodbidri | 2:1 MUX using CMOS logic | Download |
112
|
110 | SURYAPRATAP RATHORE | NATIONAL INSTITUTE OF TECHNOLOGY DELHI | Design and Performance Analysis of Low Power 1-bit Hybrid Full-Adder using 28nm CMOS Technology | Download |
113
|
111 | Suyash shrivastava | INDIAN INSTITUTE OF SCIENCE EDUCATION AND RESEARCH | LOW POWER DYNAMIC COMPARATOR | Download |
114
|
112 | Sydam Sai Teja | Vellore Institute of Technology, Vellore | Implementation of 4x4 Vedic Multiplier in 28nm CMOS Technology | Download |
115
|
113 | Tanmay Chakravorty | Thapar Institute of Engineering & Technology | Charge Pump for PLL | Download |
116
|
114 | Thoutam Rajesh | ANURAG UNIVERSITY,HYDERABAD | LOW POWER TWO STAGE OPERATIONAL AMPLIFIER | Download |
117
|
115 | VANSHIKA TANWAR | Dronacharya Group Of Institutions, Greater Noida | Four Quadrant Analog Multiplier using CMOS in 28nm Technology | Download |
118
|
116 | Vatsal Patel | Vishwakarma Government Engineering College | Dickson Charge Pump | Download |
119
|
117 | Vijay C S | Veoneer India Pvt Ltd | Design of 6T CMOS SRAM | Download |
120
|
118 | Vishal.V.Mahida | Ganpat University | Design a 2-bit magnitude comparator using 28nm CMOS Technology | Download |
121
|
119 | Yajnesh K | Mangalore Institute Of Technology & Engineering | Full Adder Using CMOS Mirror Logic | Download |
122
|
120 | Yashash Jain | IISc, Bangalore | Sub 1-V Bandgap Reference Circuit | Download |