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List of Desings under Good Category | ||||
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Sl No | Full Name | Institute / Organization name | Design Name | Certificate |
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1 | Abel Joseph John | Digital University Kerala | CMOS only Memristor | Download |
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2 | Adarsh v Parekkattil | NIT MEGHALAYA | NOR GATE SING CMOS | Download |
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3 | Aditya Agarwal | BITS Pilani KK Birla Goa Campus | NAND Gate | Download |
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4 | AKHIL HADLI | BLDEACET,Vijayapura | Three-Transistor-Two-Input-Universal-NAND-Gate | Download |
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5 | Akshay Kishor Rahangdale | Vellore Institute Of Technology, Vellore | Design 10T Full Adder using Modified Gate Diffusion Input Technique. | Download |
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6 | Amrutha V | BMSCE / HPE | FULL ADDER TOPOLOGIES AND CARRY SAVE ADDER | Download |
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7 | Anurag Singh | Analog Devices India Pvt Ltd | CMOS Full Adder Design | Download |
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10
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8 | Atyam Dhanumjaya venkata ganeshgupta | Aditya college of engineering and technology | Implementation of XOR-XNOR using 28nm technology | Download |
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9 | Atym dhanumjaya venkata ganeshgupta | Aditya college of engineering and technology | Implementation of XOR-XNOR by using 28nm technology | Download |
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10 | Ayush Agarwal | IIT BHU Varanasi | NAND gate using MOSFET's | Download |
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11 | B Kavya Shruthi | SRM Institute of Science and Technology, Kattankulathur | Design of CMOS Analog Multiplier using Gilbert Cell | Download |
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14
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12 | Baddi Sai Charan Reddy | B V Raju Institute of Technology | D_Flip-Flop-using-28nm-CMOS-Technology | Download |
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15
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13 | Balla Lalith Kumar | Gayatri Vidya Parishad College for Degree and PG Courses | CMOS Voltage Control Oscillator for Phase Locked Loop using 28nm Technology | Download |
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14 | Darsana P M | Self | Design of Half Adder Circuit in 28nm Technology | Download |
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15 | Darshan Datta Naik | RV College of Engineering | 1-Bit Full Adder using CMOS Mirror Logic | Download |
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16 | Dhanraj Choudhary | L.D. College of Engineering | Gilbert Cell | Download |
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17 | Divyank Tyagi | IIT (BHU) Varanasi | Implementation of TSPC D flip flop and Modified TSPC (MTSPC) D flip flop and its power comparison | Download |
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20
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18 | Durgasatish kocherla | Aditya college of engineering and technology | IMPLEMENTATION OF HALF ADDER USING 28nm CMOS TECHNOLOGY | Download |
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19 | GANAPATI SAHU | GIET UNIVERSITY, Gunupur, Odisha | DESIGN OF TWO INPUT NAND GATE IN 28nm CMOS TECHNOLOGY | Download |
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20 | Govinda Manohar Rathod | defence institute of advanced technology, pune | Semi-Domino Full adder | Download |
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21 | Hardik Upreti | National Institute of Technology Kurukshetra | 1 Bit ALU using Pass Transistor Logic | Download |
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22 | Harshith Pothuri | VIT AP | CMOS Schmitt trigger | Download |
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23 | Himanshu Kumar | National Institute of Science and Technology | NAND gate | Download |
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26
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24 | Hitesh | DIAT | D latch using pass transmission gate | Download |
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27
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25 | Ishika Maheshwari | ABES Engineering College | 1-Bit Full Adder using CMOS mirror logic | Download |
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28
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26 | Jayanth Nedunuri | Jyothishmathi Institute of Technology and Science | 1-Bit-Dynamic Shift Register | Download |
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29
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27 | Jeyanthi M | Thiagarajar College of Engineering | Implementation of CMOS based 1-bit Magnitude Comparator | Download |
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28 | Jitendra Singh Bisht | Bipin Tripathi Kumaon Institute of Technology | Pseudo Dynamic Latched Comparator | Download |
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29 | Karthik Chivukula | VIT Ap | CMOS Schmitt Trigger using 28nm Technology | Download |
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30 | Karthikeyan R | Anna University | Low Power Analog Neuron | Download |
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33
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31 | KARTIK BANSAL | KIET Group of Institutions | Source Follower | Download |
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34
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32 | KavithaGanapathy.N | National Institute of Technology,Puducherry | 3_Input_Nand_Gate | Download |
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33 | Kirti | IIT BHU,Varanasi | Schmitt trigger NAND GATE | Download |
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34 | Koushik Datta | National Institute of Technology Agartala | Analog voltage adder circuit using op amp in 28nm CMOS technology | Download |
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35 | Krishna Mahato | National Institute of Science and Technology, Berhampur | 2-input XOR Gate using CMOS Technology | Download |
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38
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36 | L N Saaswath | Indian Institute Of Technology, Varanasi | Low-Power 3T NAND | Download |
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39
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37 | Mayur Dattatray Parit | Shri Guru Gobind Singhji Institute Of Engineering And Technology,Nanded | 4 Input CMOS NAND gate | Download |
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38 | MOLE DASHRATH PRAKASH | Walchand College Of Engineering,Sangli. | 1Bit Full Adder | Download |
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41
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39 | N Nagamallishwar | Indian Institute of Information Technology, Tiruchirappalli. | Implementation of 2 Input NAND Gate using CMOS Technology | Download |
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40 | Navinkumar Kanagalingam | Puducherry Technological University | Transmission Gate Logic 1-bit Full Adder | Download |
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41 | P R RAHUL HEBBAR | DEFENCE INSTITUTE OF ADVANCED TECHNOLOGY | Implementation of XNOR GATE using 6 MOS transistors and 28nm Technology | Download |
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42 | PATNALA V VENKATA SIVA JYOTHI SAGAR | PUNJAB ENGINEERING COLLEGE | DESIGN OF 2:1 MULTIPLEXER USING CMOS LOGIC in 28nm | Download |
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43 | Prachi Solanki | J.C. Bose University of Science and Technology, YMCA | CMOS Used As NAND Application | Download |
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44 | Pranav Prabhu | Manipal Institute of Technology,Manipal | XOR Logic Gate using 28nm Node Technology | Download |
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45 | Premraj Vitthal Jadhav | Veermata Jijabai Technological institute, Mumbai | NAND Gate | Download |
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46 | R ROHIT KUMAR | NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY | Design Of Two Stage CMOS Operational Amplifier In 20nm Technology | Download |
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47 | Raman Rajaram Surkutlawar | Vellore Institute of Technology, Vellore | Implementation of XOR Gate Using 28nm CMOS Technology | Download |
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48 | Rambarika Bharath Chandra | defence institute of advanced technology | jk flipflop using cmos 28nm technology | Download |
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49 | Ramireddy Venkata Manish Reddy | Amrita Vishwa Vidyapeetham | 1-bit Full adder using CMOS Mirror logic | Download |
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50 | Ratan Abhinav | SRM Institute of Science & Technology | 1 Bit ALU | Download |
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51 | RISHABH VERMA | Zakir Husain college of Engineering and Technology, AMU | Design & implementaion of a 1-Bit Full Adder using 28 nm CMOS technology | Download |
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52 | Ritam Tripathi | Madan Mohan Malaviya University of Technology Gorakhpur | Cmos Schmitt Trigger | Download |
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53 | Riya Manohar Joshi | KIT's College Of Engineering, Kolhapur | Implementation of NOR GATE using CMOS | Download |
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54 | Riya S Soni | dharmsinh desai university | Implementation Of Two Stage CMOS Operational Amplifier On 28nm Technology Node | Download |
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55 | Rohan aditya | National institute of science and technology | CMOS Nor gate | Download |
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56 | Roshan Kumar | National Institute of Science and Technology, Berhampur | NAND GATE | Download |
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57 | Ruchira R | Mangalore institute of technology and engineering | Two Input XOR Gate Using CMOS 28nm Technology | Download |
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58 | Runal Kumar Panja | Institute of Radio Physics and Electronics | Current Controlled Tunable Bandwidth Low Pass Filter using 3-MOS Model | Download |
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59 | Satvik Goel | Madan Mohan Malaviya University of Technology | VCO made of CS Amplifier | Download |
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60 | Siddesh Patil | Veermata Jijabai Technological Institute (VJTI) | CMOS Implemented NOR Gate | Download |
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61 | Souhardhya Paul | Netaji Subhash Engineering College | Designing JK Flip-Flop using 28nm Architecture | Download |
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62 | Sriram G V | Sastra Deemed to be University | Two input NAND gate using CMOS technology | Download |
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63 | Sudheer kumar Pabbathi | Chaitanya Bharathi Institute of Technology | Design and Analysis of two input NAND gate in 28nm CMOS technology using synopsys custom compiler™️ | Download |
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64 | SUKHAVASI DEEPIKA 20BEC7016 | VIT Ap | CMOS Bridge Rectifier (CBR) using 28nm Technology | Download |
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65 | Swati Mavinkattimath | KLE Dr. M S Sheshgiri College of Engineering and Technology Belagavi | Half Adder | Download |
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66 | THUMMURU UDAY KIRAN | Rv-skills | Design of CMOS NAND GATE using 28nm technology | Download |
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67 | V.Adithyaa | National Institute of Technology Trichy | Design of CMOS AND Gate | Download |
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68 | Vaishnavi Jha | SRM Institute of Science and Technology, Kattankulathur | Scaled 2-Input CMOS Nand Gate using 28nm Technology | Download |
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69 | vinay kushwaha | NITK Suratkal | Dynamic Flip Flops Comparison | Download |
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70 | Vinay Saini | IIT (BHU) Varanasi | D flip flop using 28 nm CMOS | Download |