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List of Desings under Excellent Category | ||||
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Sl No | Full Name | Institute / Organization name | Design Name | Certificate |
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1 | Akula Sairam | Indian Institute of Information Technology Allahabad | Design and implementation of 4x4 Wallace tree multiplier using Sklansky | Download |
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4
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2 | Aruna Kumara Sarma K | HCL Technologies, Bengaluru, K.A | Low Power Large Range Bi-directional Level Shifter | Download |
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3 | Chandan K | Vellore Institute of Technology, Vellore | LDO Voltage Regulator with Frequency Compensation | Download |
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4 | Dilip Boidya | Tezpur University | Design of CMOS LNA with active inductor in 28nm technology | Download |
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5 | Dr. Subhash C. Arya | North Eastern Hill University, Shillong | Driver Circuit of MZI Modulator for PICs | Download |
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8
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6 | Kasetty Praveen Kumar | National Institute of Technology Puducherry | Single Stage Operational Transconductance Amplifier | Download |
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7 | Khoushikh S | Design and Analysis of a Full Adder and VCO in 28nm CMOS Technology | Download | |
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8 | Khyathi Nalluri | Indian Institute of Technology Kharagpur | 8-bit current switching DAC using binary weighted current mirrors | Download |
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11
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9 | M siva pranab reddy | Marri laxman reddy institute of technology | 4bit_adder_subtractor | Download |
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12
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10 | Mahima Saxena | ABESEC | 4-Bit Static CMOS CLA Using Modified Circuits for Carry Propagate and Generate Terms | Download |
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11 | Maliha Naaz | Muffakham Jah College of Engineering and Technology | Design and Simulation of 3 Stage Charge Pump using Synopsys Custom Compiler at 28nm Technology node | Download |
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14
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12 | MALLI CHENCHU KIRAN | Indian Institute of Information Technology,Design and Manufacturing, Kancheepuram | IMC: In-memory boolean computation using 8T SRAM | Download |
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15
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13 | Mayank Gupta | Institute of Engineering and Technology, DAVV | Two stage Opamp with Reference Circuit | Download |
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14 | P Santosh Kumar Patra | Analog Devices | Design of a low power 8×8 hybrid Dadda-Vedic multiplier | Download |
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15 | Piyush Verma | Thapar Institute of Engeneering and Technology, Punjab | Efficient-CMOS-Bandgap-Reference-Circuit | Download |
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18
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16 | Rahesh Ramachandran | PSG Institute of Technology and Applied Research | 4-bit Vedic Multiplier using GDI Technique on 28nm CMOS Technology | Download |
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17 | Rajeshwar Boyina | Graduate | High Performance 4 Bit Braun Multiplier with 22T Hybrid Full Adder | Download |
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18 | Sanchith V M | NA | Design of 4-bit ALU | Download |
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21
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19 | Shabbar Vejlani | Individual | Axon HillLock Neuromorphic Circuit Implementation | Download |
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22
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20 | Soham Sen | Amity University Kolkata | LDO Voltage Regulator | Download |
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21 | Soma Venkata Maharshi | National Institute of Technology-Tiruchirappalli | 8Bit CMOS Wallace Tree Multiplier | Download |
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24
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22 | Sonu Agrawal | Vellore Institute of Technology Vellore | Implementation of D-Flip Flop Using 28nm CMOS Technology | Download |
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23 | Subham Mohapatra | National Institute of Technology Karnataka | 3-bit Wallace tree Multiplier | Download |
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26
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24 | sudarsh joshi | thapar institute of engineering and technology | A High Speed Low Power Comparator with Composite Cascode Pre amplification. | Download |
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25 | Sumanyu Singh | Indian Institute of Information Technology, Allahabad | True Single Phase Clock(TSPC) D Flip Flop Design | Download |
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28
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26 | SUNIT PUJARI | IIIT HYDERABAD | Implementation of LDO using two stage operational amplifier using 28nm CMOS technology | Download |
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27 | Tanya Bansal | Maharaja Surajmal Institute of Technology | Implementation of a 4-bit Universal Shift Register | Download |
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28 | Vaibhav Mishra | Vellore Institute of Technology, Vellore | High-speed-dynamic-comparator-28nm-process | Download |
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29 | Vignesh Bharadwaj | Birla Institute of Technology and Science, Pilani, Hyderabad Campus | Approximate Compressor for error-resilient Multiplications | Download |
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30 | Vinod Kumar Yadav | Government Girls Polytechnic Gorakhpur | Non-overlapping clock generator for micro scale energy harvesting applications in 28nm CMOS technology | Download |